Abstract:
This paper proposes a model of PCB traces for high speed digital systems. The adopted approach involves predetermined geometry using direct discretization of transmission lines. Initially, the proposed methodology involves computing the line propagation delay by employing its geometry with associated empirical equations. The initial procedure paves the way to design a Lattice diagram which depicts multiple reflections that the signal underwent due to impedance mismatches between transmission lines and loads. Subsequent computations of electrical model parameters were further done. Simulation results using Multisim software illustrated a favorable performance with a time delay of 1.42 ns and an equivalent electrical model of 10 lumped LC cells. The time delay between input and output signal obtained from the simulation was approximately 15.152 ns corresponding to the time it took for a transmitted signal to reach a steady state which further signifies good performance of our proposed method.
